Semiconductor device and manufacturing method thereof

ABSTRACT

The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This application is a division of application Ser. No.09/657,839, filed Sep. 7, 2000, now pending, and based on JapanesePatent Application No. 11-252827, filed Sep. 7, 1999 and Japanese PatentApplication No. 2000-166234, filed Jun. 2, 2000 including thespecification, drawings, claims and abstract, all of which areincorporated herein by reference in their entirety. This applicationclaims only subject matter disclosed in the parent application andtherefore presents no new matter.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to semiconductor device having amemory cell portion and manufacturing method thereof, and moreparticularly, to a semiconductor device directed to lowering of theresistance of the connection portion of a field effect transistor and amanufacturing method thereof.

[0004] 2. Description of the Related Art

[0005] Semiconductor devices using a MOS (Metal Oxide Semiconductor)field effect transistor have been developed in various fields andimplemented as a device having multiple functions as the technique ofreducing the size and the technique of high density integration haveadvanced. As a typical semiconductor device having multiple functions, asemiconductor device including both a DRAM (Dynamic Random AccessMemory) and a logic is known. Disadvantages associated with the multiplefunction semiconductor device will be now described.

[0006]FIGS. 1A and 1B are cross sectional views showing the memory cellportion and peripheral circuit portion of a conventional DRAM. As shownin FIGS. 1A and 1B, in the peripheral circuit portion, a MOS transistorhaving an n type diffusion layer and a p type diffusion layer is formed.As shown in FIG. 1A, a p well 242 is formed on the surface of asemiconductor substrate 241, and a plurality of element isolation oxidefilms 243 are formed on the surface of the p well 242. Thus, a memorycell portion 260 and a peripheral circuit portion 270 are partitionedand there are a plurality of element regions in the memory cell portion260 and the peripheral circuit portion 270. At the surface of the p well242 in an element region in the memory cell portion 260, an n typediffusion layer 244 is formed. At the surface of the p well 242 in anelement region in the peripheral circuit portion 270, an n typediffusion layer 274 is formed. The n type diffusion layer 274 in theperipheral circuit portion 270 is formed to a position deeper than the ntype diffusion layer 244 in the memory cell portion 260. An interlayerinsulating film 246 is formed at the upper surfaces of these elementregions. In the interlayer insulating film 246, there is a memory cellportion contact 247 connected to the n type diffusion layer 244 andfilled with a phosphorus-doped polysilicon plug 250 formed of aphosphorus-doped polysilicon film. Also in the interlayer insulatingfilm 246, there is a peripheral circuit portion contact 248 connected tothe n type diffusion layer 274 in the peripheral circuit portion 270,and a phosphorus-doped polysilicon plug 251 formed in the same processis filled therein. A metal interconnection 255 connected to thesephosphorus-doped polysilicon plugs 250 and 251 is also formed.

[0007] In FIG. 1B, a p type diffusion layer 245 is formed on the surfaceof the p well 242 in the peripheral circuit portion 270. An interlayerinsulating film 266 is formed on the interlayer insulating film 246 andthe metal interconnection 255. A peripheral circuit portion contact 258reaching the p type diffusion layer 245 is formed in the interlayerinsulating films 266 and 246, and a metal plug 254 is filled therein. Ametal plug 256 connected to the metal interconnection 255 is formed inthe interlayer insulating film 266. Similarly to FIG. 1A, in the memorycell portion 260, a phosphorus-doped polysilicon plug 250 is filled inthe memory cell contact portion 247 provided in the interlayerinsulating film 246, and is connected to the n type diffusion layer 244.

[0008] The phosphorus-doped polysilicon plug 250 normally has the sameconductivity type as that of the n type diffusion layer 244. As aresult, when an n type polysilicon plug of the same conductivity type asthe polysilicon plug in the memory cell portion 260 is formed in theperipheral circuit portion contact 258 on the p type diffusion layer 245in the peripheral circuit portion 270, a pn junction forms andapplication of a voltage across the region between the n typepolysilicon plug and the p type diffusion layer causes an undesirablerectifying effect therebetween. Therefore, an n type polysilicon plugcannot be used for the peripheral circuit portion contact 258, and ametal plug is used instead. Thus, the p type diffusion layer 245 in theperipheral circuit portion is connected to the upper metal filminterconnection 265 through the metal plug 254 filling the peripheralcircuit portion contact 258 and then connected to the metalinterconnection 255 through the metal plug 256 provided in theinterlayer insulating film 266.

[0009] Note however that as the size of a memory cell portion contact isreduced with reduction in the size of elements, the resistance of the ntype polysilicon plug increases, which could cause a fault in theoperation of cells. A metal plug may be used instead of the n typepolysilicon plug for the contact of the memory cell portion, but the useof the metal plug increases diffusion layer leakage. As a result, ametal plug cannot be used for forming the memory cell portion contactunlike for the peripheral circuit portion contact.

SUMMARY OF THE INVENTION

[0010] It is an object of the present invention to provide amultifunction semiconductor device including memory cells with a reducedsize, having a low resistance contact plug without diffusion layerleakage in the memory cell portion and a low resistance contact plug inthe peripheral circuit portion of the memory cell portion.

[0011] A semiconductor device according to a first aspect of the presentinvention includes: semiconductor substrate; an element formed on saidsubstrate; an interlayer insulating film formed on said semiconductorsubstrate; a first opening provided in said interlayer insulating filmand reaching the surface of said semiconductor substrate; a secondopening having a larger opening size than the first opening; a firstplug having a lower conductive silicon film filled within a lowerportion of said first opening and a metal film filled within an upperportion of said first opening; and a conductive, second plug filledwithin said second opening.

[0012] A semiconductor device according to a second aspect of thepresent invention includes: a semiconductor substrate; an element formedon said substrate; a gate insulating film formed on said semiconductorsubstrate; first and second gate electrodes formed on said gateinsulating film; a sidewall insulating film formed on a sidewall of saidgate electrode; an interlayer insulating film covering an upper surfaceof said semiconductor substrate including said gate electrode and saidsidewall insulating film; first and second openings provided in saidinterlayer insulating film and reaching the surface of saidsemiconductor substrate; and conductive, first and second plugs filledwithin said first and second openings, respectively, said first gateelectrode being formed at a first interval smaller than twice thethickness of said sidewall insulating film, and said second gateelectrode being formed at a second interval larger than twice thethickness of said sidewall insulating film.

[0013] In the semiconductor devices according to the first and secondaspect of the present invention, the first plug has a conductive siliconfilm filled within a lower layer portion of the first opening and theplug upper layer metal film filled within an upper layer and the secondplug has conductive film filled within the second opening and can bedirectly connected to a diffusion layer. Therefore, the resistance ofsecond plug reduced. In addition the device will not degrade the leakagecharacteristic in the first plug formed in a memory cell.

[0014] A method of manufacturing the semiconductor device according to afirst aspect of the present invention includes the steps of: formingfirst and second diffusion layers on a surface of a semiconductorsubstrate; forming an interlayer insulating film on said semiconductorsubstrate including said first and second diffusion layers; formingfirst and second openings in a region of the interlayer insulating filmon said first diffusion layer and a region of the interlayer insulatingfilm on said second diffusion layer, respectively to expose surfaces ofsaid first and second diffusion layers; depositing a conductive siliconfilm on said semiconductor substrate; etching back said conductivesilicon film to form a lower portion of a first plug in a lower portionof said first opening while at the same time removing the conductivesilicon film at the bottom of said second opening to expose a surface ofsaid second diffusion layer; and depositing a metal film on saidsemiconductor substrate including said first and second openings,filling said first and second openings with said metal film to form anupper portion of said first plug on said lower conductive silicon plugin said first opening while at the time forming a second plug by saidmetal film filling within said second opening with the sidewallconductive silicon film.

[0015] A method of manufacturing the semiconductor device according to asecond aspect of the present invention includes the steps of: formingfirst and second diffusion layers on a surface of a semiconductorsubstrate; forming an interlayer insulating film on said semiconductorsubstrate including said first and second diffusion layers; forming afirst opening in a region of the interlayer insulating film on saidfirst diffusion layer to expose a surface of said first diffusion layer;depositing a conductive silicon film to fill a lower portion of saidfirst opening with said conductive silicon film, thereby forming a lowerportion of a first plug; depositing an upper metal film to fill an upperportion of said first opening with said upper metal film, therebyforming an upper portion of said first plug; forming a second opening ina region of the interlayer insulating film on said second diffusionlayer to expose a surface of said second diffusion layer; and depositinga metal film on said semiconductor substrate including said secondopening to fill said second opening with said metal film, therebyforming a second plug.

[0016] A method of manufacturing the semiconductor device according to athird aspect of the present invention includes the steps of: formingfirst and second diffusion layers on a surface of a semiconductorsubstrate; forming an interlayer insulating film on said semiconductorsubstrate including said first and second diffusion layers; formingfirst and second openings in a regions in the interlayer insulating filmon said first and second diffusion layers, respectively and exposingonly a surface of said first diffusion layer; depositing a conductivesilicon film to fill a lower portion of said first opening with theconductive silicon film, thereby forming a lower portion of a firstplug; exposing a surface of said second diffusion layer at the bottom ofsaid second opening; and depositing a metal film on said semiconductorsubstrate including said first and second openings, filling an upperportion of said first opening with said metal film to form an upperportion of said first plug, while at the same time filling said secondopening with said metal film to form a second plug.

[0017] A method of manufacturing the semiconductor device according to afourth aspect of the present invention includes the steps of: formingfirst and second gate electrodes on a semiconductor substrate, thedistance between said first gate electrodes being narrow than thedistance between said second gate electrodes; forming a first sidewallinsulating film at sidewalls of said first and second gate electrodes;forming a first diffusion layer on said semiconductor substrate usingsaid first gate electrode and said first sidewall insulating film as amask and forming a second diffusion layer on said semiconductorsubstrate using said second gate electrode and said first sidewallinsulating film as a mask; forming a second sidewall insulating film onsaid first sidewall insulating film; depositing an etching stopper film;forming an interlayer insulating film on said etching stopper film;etching said interlayer insulating film, said etching stopper film andsaid first and second sidewall insulating film so as to form a firstopening in a region on said first diffusion layer exposing a surface ofsaid first diffusion layer and a second opening in a region on saidsecond diffusion layer exposing said etching stopper film; depositing aconductive silicon film to fill a lower portion of said first openingwith the conductive silicon film, thereby forming a lower portion of afirst plug; removing said etching stopper film at the bottom of saidsecond opening to expose a surface of said second diffusion layer; anddepositing a metal film on said semiconductor substrate including saidfirst and second openings, filling an upper portion of said firstopening with said metal film to form an upper portion of said first plugin said first opening while at the same time filling said second openingwith said metal film to form a second plug in said second opening.

[0018] In the methods of manufacturing the semiconductor deviceaccording to the first to fourth aspect of the present invention, theconductive silicon film is any of a polysilicon film, an amorphoussilicon film, an epitaxial layer, and a silicon-germanium compoundcrystal. If the conductive silicon film is an amorphous silicon film,the amorphous silicon film may be reformed into a polysilicon film afterthe first and second openings are filled with the metal film.

[0019] The nature, principle, and utility of the invention will becomemore apparent from the following detailed description when read inconjunction with the accompanying drawings in which like parts aredesignated by like reference numerals or characters.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings:

[0021]FIG. 1A and 1B are cross sectional views of a conventionalsemiconductor device;

[0022]FIGS. 2A to 2C are cross sectional views showing a method ofmanufacturing a semiconductor device according to a first embodiment ofthe present invention in the order of the manufacturing steps;

[0023]FIGS. 3A to 3C are cross sectional views showing a method ofmanufacturing a semiconductor device according to a second embodiment ofthe present invention in the order of the manufacturing steps;

[0024]FIG. 4 is a cross sectional view of a semiconductor deviceaccording to a third embodiment of the present invention;

[0025]FIG. 5 is a cross sectional view of a semiconductor deviceaccording to a fourth embodiment of the present invention;

[0026]FIGS. 6A to 6C are cross sectional views showing a method ofmanufacturing a semiconductor device according to a fifth embodiment ofthe present invention in the order of the manufacturing steps;

[0027]FIGS. 7A to 7C are cross sectional views showing the method ofmanufacturing the semiconductor device according to the fifthembodiment, showing steps following those in FIG. 6 in the order of themanufacturing steps;

[0028]FIG. 8A to 8C are cross sectional views showing the method ofmanufacturing the semiconductor device according to the fifthembodiment, showing the steps following those in FIGS. 7 in the order ofthe manufacturing steps; and

[0029]FIG. 9 is a cross sectional view of a semiconductor deviceaccording to a sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Semiconductor devices according to embodiments of the presentinvention and manufacturing methods thereof will be now described indetail in conjunction with the accompanying drawings. Basic features ofthe present invention will be described first. In a semiconductor deviceaccording to the present invention, in contact holes formed on diffusionlayers in a memory cell and the peripheral circuit of the memory celland filled with a metal film, the metal film and the diffusion layer onthe substrate surface are directly connected at the bottom of thecontact in the peripheral circuit portion. Meanwhile, the metal film andthe diffusion layer on the substrate surface are connected through apolysilicon film at the bottom of the contact in the memory cell.

[0031] More specifically, when there are a region with a small intervalbetween adjacent gate electrodes for example in the memory cell portionand a region with a large interval between adjacent gate electrodes forexample in the peripheral circuit portion in the chip, a silicon layeris formed at the bottom in the contact hole in the region with the smallinterval, and a metal plug is formed both in an upper layer of thesilicon layer and the contact hole in the region with the largeinterval.

[0032] There are roughly the following two kinds of manufacturingmethods for the semiconductor device according to the present invention.

[0033] According to the first manufacturing method, when contact holesare provided in an interlayer insulating film on a substrate, a contactin a memory cell is provided in a region where a sidewall insulatingfilm region having sidewall insulating films of adjacent gate electrodesjoined with one another, a stopper nitride film, and an interlayerinsulating film are formed in this order from the side of the substrate.A contact in a peripheral circuit portion is formed in a region where astopper nitride film and an interlayer insulating film are formed inthis order from the side of the substrate. In the contact in the memorycell, at the time point at which a diffusion layer is exposed, thediffusion layer is not exposed at the bottom of the contact in theperipheral circuit portion and covered with a stopper nitride film.Utilizing these different contact opening states, a conductive siliconfilm is selectively deposited only at the bottom of the contact in thememory cell. Then, a plug of a metal film entirely fills both contactholes.

[0034] According to the second manufacturing method, when contact holesare provided in an interlayer insulating film on a substrate, theopening width of a contact in a peripheral circuit is formed to belarger than that of a contact in a memory cell. Then, a polysilicon filmdeposited on the entire surface is etched back, so that a plug of thepolysilicon film is formed at the bottom of the contact in the memorycell. At this time, in the contact in the peripheral circuit having thelarger opening width, the polysilicon film is formed at the bottom andsidewall. Only the polysilicon film at the bottom is removed to expose asurface of the substrate at the contact bottom, and a sidewall portionis formed on the sidewall on the bottom side of the contact. Then, aplug of a metal film entirely fills the contact holes.

[0035] Regarding the sizes of the contacts in the memory cell and theperipheral circuit according to the first manufacturing method, thecontact in the peripheral circuit is formed to have a larger openingwidth than that of the contact in the memory cell similarly to thesecond manufacturing method.

[0036] A first embodiment of the present invention will be nowdescribed. FIG. 2C is a cross sectional view of a semiconductor deviceaccording to the present embodiment. As shown in FIG. 2C, a p well 2 isformed on the surface of a silicon substrate 1. An element isolationoxide film 3 to partition a memory cell portion 20 and a peripheralcircuit portion 30 and isolate elements formed in these regions isformed. In regions of the surface of the semiconductor substrate 1 inthe memory cell portion 20 and the peripheral circuit portion 30partitioned by the element isolation oxide film 3, an n type diffusionlayer 4 and a p type diffusion layer 5 are formed, respectively. Notethat the p type diffusion layer 5 in the peripheral circuit portion 30is formed to a position deeper than the n type diffusion layer 4 in thememory cell portion 20. An interlayer insulating film 6 is formed on thepart of the semiconductor substrate 1 where these diffusion layers areformed. In the interlayer insulating film 6, there are formed a memorycell portion contact (first opening) 7 and a peripheral circuit portioncontact (second opening) 8 connected to the n type diffusion layer 4 inthe memory cell portion 20 and the p type diffusion layer 5 in theperipheral circuit portion 30, respectively. A phosphorus-dopedpolysilicon plug (lower portion of a first plug) 10 fills a lowerportion of the memory cell portion contact 7. An upper metal plug 13fills an upper portion of the memory cell portion contact 7. Aphosphorus-doped polysilicon sidewall (conductive sidewall silicon film)11 is formed on the sidewall of the peripheral circuit portion contact 8on the bottom side. The other region is filled with a metal plug 14. Ametal interconnection 15 connected to the upper metal plug (upperportion of a first plug) 13 and the metal plug 14 is formed on theinterlayer insulating film 6.

[0037] A method of manufacturing the semiconductor device according tothe present embodiment will be now described. FIGS. 2A to 2C are crosssectional views showing the method of manufacturing the semiconductordevice according to the present embodiment in the order of themanufacturing steps. FIG. 2A shows the memory cell portion 20 and theperipheral circuit portion 30 in the semiconductor device where the pwell 2, the element isolation insulating film 3, a gate oxide film (notshown), a gate electrode (not shown), and the n type diffusion layer 4in the memory cell portion 20 and the p type diffusion layer 5 in theperipheral circuit portion 30 to be source/drain diffusion regions havebeen formed on the surface of the semiconductor substrate 1. Note thatthe n type diffusion layer in the peripheral circuit portion 30 is notshown. The p type diffusion layer 5 and the n type diffusion layer inthe peripheral circuit portion 30 are formed at a position deeper thanthe n type diffusion layer in the memory cell portion 20. The interlayerinsulating film 6 is formed on the semiconductor substrate 1 having suchelements formed thereon. Then, a memory cell portion contact 7 and aperipheral circuit portion contact 8 are formed in the interlayerinsulating film 6 on the n type diffusion layer 4 and p type diffusionlayer 5 in the memory cell portion 20 and the peripheral circuit portion30, respectively to expose the diffusion layers formed on the surface ofthe semiconductor substrate 1. At this time, the peripheral circuitportion contact 8 is formed to have an opening width larger than that ofthe memory cell portion contact 7. A phosphorus-doped polysilicon(conductive silicon film) 9 is grown on the semiconductor substrate 1.The thickness of the phosphorus-doped polysilicon 9 at this time is setto be smaller than ½ the opening width of the peripheral circuit portioncontact 8 and larger than ½ the opening width of the memory cell portioncontact 7.

[0038] Then, as shown in FIG. 2B, the phosphorus-doped polysilicon 9 isetched back to form a phosphorus-doped polysilicon plug 10 at the bottomof the memory cell portion contact 7. At this time, the phosphorus-dopedpolysilicon 9 at the bottom of the peripheral circuit portion contact 8is removed to expose a surface of the p diffusion layer 5 at the innerbottom surface of the contact. Thus, a phosphorus-doped polysiliconsidewall 11 is formed at the bottom sidewall of the peripheral circuitportion contact 8. The phosphorus-doped polysilicon 9 is set to havesuch a thickness to entirely fill the memory cell portion contact 7while not entirely filling the peripheral circuit portion contact 8 butbeing deposited on the sidewall and the bottom surface.

[0039] As shown in FIG. 2C, a metal film 12 is deposited on the entiresurface followed by etch back or CMP (Chemical Mechanical Polishing) toprovide an upper metal plug 13 and a metal plug 14 in the memory cellportion contact 7 and the peripheral circuit portion contact 8,respectively. Then, a metal interconnection 15 connected to the uppermetal plug 13 and the metal plug 14 is formed.

[0040] According to the present embodiment, using the difference betweenthe opening widths of the contacts in the memory cell portion 20 and theperipheral circuit portion 30, a polysilicon film plug can be formedonly at the bottom of the memory cell portion contact 7. The peripheralcircuit portion contact 8 can be directly connected to the p typediffusion layer 5 and the n type diffusion layer by the metal film plug14. Therefore, the contacts can be formed on the n type diffusion layer4 in the memory cell portion 20, and on the n type and p type diffusionlayers in the peripheral circuit portion 30 while at the same time aconductive material can be filled within the contacts in a series ofprocess steps without additional lithography steps. In addition, whilethe resistance of the memory cell portion contact 7 is reduced, themanufacturing process can be simplified. The arrangement ofinterconnections in the peripheral circuit portion 30 can be alsosimplified, so that the restriction on size reduction in the peripheralcircuit portion 30 can be removed. Furthermore, the series of processsteps will not degrade the leakage characteristic in the memory cellportion contact 7.

[0041] A second embodiment of the present invention will be nowdescribed. FIG. 3C is a cross sectional view of a semiconductor deviceaccording to the present embodiment. As shown in FIG. 3C, similarly tothe first embodiment, formed on the surface of a semiconductor substrate41 are a p well 42, an element isolation insulating film 43, an n typediffusion layer 44 in a memory cell portion 60, an n type diffusionlayer (not shown) and a p type diffusion layer 45 in a peripheralcircuit portion 70. The elements are formed in the memory cell portion60 and the peripheral circuit portion 70. An interlayer insulating film46 is formed on the semiconductor substrate 41 having the elements thusformed thereon, and there are a memory cell portion contact (firstopening) 47 and a peripheral circuit portion contact (second opening) 48reaching the n type diffusion layer 44 and the p type diffusion layer45, respectively. Furthermore, the memory cell portion contact 47 isfilled with a lower phosphorus-doped polysilicon plug (lower portion ofa first plug) 50 and an upper metal plug (upper portion of the firstplug) 53. The peripheral circuit portion contact 48 is filled with ametal plug (a second plug) 54. A metal interconnection 55 connected tothe upper metal plug 53 and the metal plug 54 is formed on theinterlayer insulating film 46.

[0042] A method of manufacturing the semiconductor device according tothe present embodiment will be now described. FIGS. 3A to 3C are crosssectional views showing the method of manufacturing the semiconductordevice according to the present embodiment in the order of themanufacturing steps. FIG. 3A shows the state after the interlayerinsulating film 46 has been grown on a semiconductor substrate having agate oxide film, a gate electrode, a source/drain diffusion layer andthe like formed thereon similarly to the first embodiment. Morespecifically, as shown in FIG. 3A, formed on the semiconductor substrate41 are the p well 42, the element isolation oxide film 43, the n typediffusion layer 44 in the memory cell portion 60, the p type diffusionlayer 45 in the peripheral circuit portion 70 (with the n type diffusionlayer in the peripheral circuit portion 70 not being shown), and theinterlayer insulating film 46. The p type diffusion layer 45 and the ntype diffusion layer in the peripheral circuit portion 70 are formed atpositions deeper than the n type diffusion layer in the memory cellportion 60. Then, a memory cell portion contact 47 reaching the n typediffusion layer 44 is formed in the interlayer insulating film 46, and aphosphorus-doped silicon film is deposited. Then, a phosphorus-dopedpolysilicon plug 50 is formed at the bottom of the memory cell portioncontact 47 by etch back. A metal layer is further deposited followed byetch back or CMP to form an upper metal plug 53.

[0043] As shown in FIG. 3B, a peripheral circuit portion contact 48reaching the p type diffusion layer 45 is formed in the interlayerinsulating film 46. Then, a metal film is deposited, followed by etchback or CMP to form a metal plug 54.

[0044] Then, as shown in FIG. 3C, a metal interconnection 55 connectedto the upper metal plug 53 in the memory cell portion 60 and the metalplug 54 in the peripheral circuit portion 70 is formed.

[0045] In the method of manufacturing the present embodiment, thecontacts in the memory cell portion 60 and the peripheral circuitportion 70 are filled with a conductive material, so that the leakagecharacteristic of the memory cell portion contact 47 will not bedegraded. The opening width of the peripheral circuit portion contact 48does not have to be restricted to a size larger than twice the width ofthe phosphorus-doped polysilicon film unlike the first embodiment, sothat the size of the peripheral circuit portion 70 as well as the sizeof the memory cell portion 60 can be reduced.

[0046] Note that according to the present embodiment, a phosphoruspolysilicon film is deposited on the memory cell portion contact 47 andetched back to form the phosphorus-doped polysilicon plug 50. However,the silicon plug may be formed by selective epitaxial growth to thememory cell portion contact 47 in place of the above method.

[0047] A third embodiment of the present invention will be nowdescribed. FIG. 4 is a cross sectional view of the semiconductor deviceaccording to the present embodiment. According to the presentembodiment, a phosphorus-doped amorphous silicon film is used instead ofthe phosphorus-doped polysilicon film used in the first embodiment. Notethat in the third embodiment shown in FIG. 4, the same elements as thosein the first embodiment shown in FIG. 2 are denoted by the samereference characters and a detailed description is not provided.

[0048] As shown in FIG. 4, a memory cell portion 100 and a peripheralcircuit portion 110 are formed on a semiconductor substrate 1. In aninterlayer insulating film 6 for the memory cell portion 100 and theperipheral circuit portion 110, a memory cell portion contact 87reaching an n type diffusion layer 4 and a peripheral circuit portioncontact 88 reaching a p type diffusion layer 5 and an n type diffusionlayer (not shown) are formed, respectively similarly to the firstembodiment. Then, phosphorus-doped amorphous silicon is deposited on thesemiconductor substrate 1 including these contact holes and etched back.Thus, a phosphorus-doped amorphous silicon plug (lower portion of afirst plug) 90 is formed at the bottom of the memory cell portioncontact (first opening) 87, and a phosphorus-doped amorphous siliconsidewall 91 is formed on the sidewall at the bottom of the peripheralcircuit portion contact (second opening) 88. At this time, in theperipheral circuit portion contact portion 88, a surface of the p typediffusion layer 5 at the bottom in the contact is exposed. A metal filmis then filled within the upper portion of the memory cell portioncontact 87 and the peripheral circuit portion contact 88. The metal filmmay be a layered metal film including for example a lower layer of Ti,an upper of TiN (hereinafter referred to as TiN/Ti), barrier film 96thereon, and a film of a refractory metal such as tungsten furtherthereon. After the layered metal film is deposited, etch back or CMP isperformed to provide an upper metal plug 93 and a metal plug 94 in thememory cell contact 87 and the peripheral circuit portion contact 88,respectively. Then, in the memory cell portion 100, the surface of the ntype diffusion layer 4 and Ti are allowed to react with one anotherthrough the phosphorus amorphous silicon plug 90 by annealing, and a Tisilicide film is formed. Similarly, in the peripheral circuit portion110, the surface of the p type diffusion layer 5 and Ti are allowed todirectly react with one another to form a Ti silicide film. Then, ametal interconnection 95 is formed and thus the metal interconnection 95and the upper surfaces of the upper metal plug 93 and the metal plug 94are connected.

[0049] As in the present embodiment, when a plug of an amorphous siliconfilm is used for a contact portion, the amorphous silicon film may bereformed into a polysilicon film having crystallinity by annealing, inother words, the amorphous silicon film may be formed into a materialhaving lower resistance.

[0050] In this embodiment, in addition to the effects of the firstembodiment, the connection resistance of the diffusion layers in thememory cell portion and the peripheral circuit portion and the metalplugs may be further reduced.

[0051] Note that in this embodiment, the phosphorus-doped amorphoussilicon film, the barrier film and the refractory metal film arecombined, but it should be understood that a combination of aphosphorus-doped polysilicon film, a barrier film and a refractory metalfilm may be employed.

[0052] A fourth embodiment of the present invention will be nowdescribed. FIG. 5 is a cross sectional view of a semiconductor deviceaccording to the present embodiment. In place of the phosphorus-dopedpolysilicon film according to the second embodiment, a phosphorus-dopedamorphous silicon film is used, and a layered film of a TiN/Ti barrierfilm and a refractory metal film such as a tungsten film is used. Notethat in the fourth embodiment shown in FIG. 5, the same elements asthose in the second embodiment shown in FIG. 3 are denoted by the samereference characters and a detailed description is not provided.

[0053] As shown in FIG. 5, after a memory cell portion contact 127reaching an n type diffusion layer 44 is formed in an interlayerinsulating film 46 in a memory cell portion 140, a phosphorus-dopedamorphous silicon film is deposited and etched back to form aphosphorus-doped amorphous silicon plug (lower portion of a first plug)130 at the bottom of the memory cell portion contact (first opening)127. Then, a TiN/Ti barrier film 136 is deposited, and then a refractorymetal film such as a tungsten film is deposited on the barrier film 136.An upper metal plug 133 is formed in the memory cell portion contact 127by etch back or CMP.

[0054] Then, a peripheral circuit portion contact (second opening) 128reaching a p type diffusion layer 45 and an n type diffusion layer (notshown) is formed in an interlayer insulating film 46 in a peripheralcircuit portion 150. A barrier film 146 of TiN/Ti or the like isdeposited, and a refractory metal film such as a tungsten film isdeposited followed by etch back or CMP to form a metal plug 134 in theperipheral circuit portion contact 128. Then, in the memory cell portion140, the surface of the n type diffusion layer 44 and Ti are allowed toreact with one another through the phosphorus-doped amorphous siliconplug 130, and a Ti silicide film is formed. In the peripheral circuitportion 150, the surface of the p type diffusion layer 45 and the Ti areallowed to directly react to form a Ti silicide film. A metalinterconnection 135 connected to the upper surfaces of the upper metalplug 133 and the metal plug 134 is formed on the interlayer insulatingfilm 46.

[0055] It should be understood that though the phosphorus-dopedamorphous silicon film, the barrier film and the refractory metal filmare combined in the above-described case, a combination of aphosphorus-doped polysilicon film, a barrier film and a refractory metalmay be employed.

[0056] Also in the present embodiment, the phosphorus-doped amorphoussilicon film is deposited on the memory cell portion contact and etchedback to form the phosphorus-doped amorphous silicon plug, but selectivegrowth of phosphorus-doped epitaxy to the memory cell contact may beemployed to form such a silicon plug similarly to the second embodiment.

[0057] According to the present embodiment, in addition to the effectsof the second embodiment, the connection resistance of the diffusionlayers in the memory cell portion 140 and the peripheral circuit portion150 and the metal plug can be further reduced.

[0058] A fifth embodiment of the present invention will be nowdescribed. FIG. 8C is a cross sectional view of a semiconductor deviceaccording to the present embodiment. As shown in FIG. 8C, formed on thesurface of a semiconductor substrate 161 are a p well 162, a memory cellportion 180, a peripheral circuit portion 190 and an element isolationinsulating film 163 to isolate a plurality of elements formed in theseregions. An n type diffusion layer 164, an n type diffusion layer 165and a p type diffusion layer (not shown) are formed on the surface ofthe p well 162 in regions of the memory cell portion 180 and theperipheral circuit portion 190. A gate insulating film 186 is formed onthe semiconductor substrate 161 in a region between these diffusionlayers, and gate electrodes 181 and 182 are formed on the gateinsulating film 186 in the memory cell portion 180 and the peripheralcircuit portion 190, respectively. At the sidewalls of the gateelectrodes 181 and 182, a first sidewall insulating film 183 and asecond sidewall insulating film 184 on the outer side of the firstsidewall insulating film 183 are formed. A stopper film (etching stopperfilm) 185 and an interlayer insulating film 166 are formed on the entiresurface of the semiconductor substrate 161 having these elements formedthereon. A memory cell portion contact (first opening) 167 is formedthrough a sidewall interlayer insulating film on the n type diffusionlayer 164 in the memory cell portion 180, the stopper film 185 and theinterlayer insulating film 166. A lower portion of the contact is filledwith a silicon film (lower portion of first plug) 170 and an upperportion is filled with an upper metal plug (upper portion of first plug)173. The silicon film 170 has the same conductivity type as that of then type diffusion layer 164 connected with the contact. The silicon film170 is activated, and the impurity concentration of the activatedsilicon film 170 may be in the range from 1×10¹⁸ to 10²¹/cm³. If theconcentration is low, the contact hole serves as external parasiticresistance for the source/drains of the MOSFET to which it is connected.The external parasitic resistance reduces the electric field in thesource-drain region, so that the threshold voltage can be prevented frombeing unnecessarily lowered by the short channel effect. If theconcentration is high, the resistance is lowered, and therefore theparasitic resistance described above is expected to be low.

[0059] In the peripheral circuit portion contact 190, a peripheralcircuit portion contact hole (second opening) 168 is formed through thestopper film 185 and the interlayer insulating film 166 on the n typediffusion layer 165, and a metal plug (second plug) 174 is filledtherein.

[0060] The metal film filled in the holes of the memory cell contact 167and the peripheral circuit portion contact 168 is of a metal such astitanium and tantalum which reacts with silicon to form silicide and adiffusion barrier film against silicon. A metal interconnection 175connected to the upper metal plug 173 and the metal plug 174 forconnecting elements is formed on the interlayer insulating film 166.

[0061] In the present embodiment, the interval between the gateelectrodes 181 formed in the memory cell portion 180 is small, while theinterval between adjacent gate electrodes 182 in the peripheral circuitportion 190 is large. The device size to achieve the state can bedefined by the following expressions 1 to 3:

d1<d2  (1)

2×d1+2×d2>Dga  (2)

[0062] and

2×d2+2×d2<Dgb  (3)

[0063] wherein the gate interval in the memory cell portion 180 is Dga,the gate interval in the peripheral circuit portion 190 is Dgb, thethickness of the first sidewall insulating film 183 (first interlayerinsulating film) is d1, and the thickness of the second sidewallinsulating film 184 (second interlayer insulating film) is d2.

[0064] A method of manufacturing the semiconductor device according tothe present embodiment will be now described. FIGS. 6A to 6C to 8A to 8Care cross sectional views showing the method of manufacturing thesemiconductor device according to the present embodiment in the order ofthe manufacturing steps.

[0065] As shown in FIG. 6A, a p well 162 is formed on the surface of ann type semiconductor substrate 161, and an element isolation insulatingfilm 163 is formed. The element isolation insulating film 163 can beformed for example by the trench isolation technique, according to whicha trench for example is formed and a silicon oxide film is filled in thetrench.

[0066] Note that according to the present embodiment, the p well 162 isformed in the semiconductor substrate 161, but a p or n well may beformed as required. The well is formed by implanting an impurity by highenergy ion implantation, and a desired impurity distribution is given bythermal treatment. Then, the surface of the semiconductor substrate 161is oxidized, and a thin silicon oxide film is formed as a gateinsulating film 186. The thickness of the silicon oxide film ispreferably in the range from 1 to 7 nm. The gate insulating film 186 maybe silicon nitride film. Furthermore, in order to set the threshold ofthe MOSFET, the impurity concentration at the surface of thesemiconductor substrate 161 is adjusted.

[0067] A gate electrode is then formed. A polysilicon film for exampleis formed as the gate electrodes 181, 182 at a position on the gateinsulating film 186 by a known technique. Here, the gate electrodes 181,182 may have a layered structure including metal and polysilicon. Gateelectrodes 181 formed in a memory cell portion 180 has a higher gateelectrode density than gate electrodes 182 formed in a peripheralcircuit portion 190. This means that if memory cells are arrangedregularly like DRAM memory cells, the arrangement pitch of the gateelectrodes 181 in the memory cell portion 180 is smaller than thearrangement pitch of the gate electrodes 182 in the peripheral circuitportion 190.

[0068] A first interlayer insulating film is formed on the entiresurface, and the first interlayer insulating film is etched back byanisotropic dry etching to form a first sidewall insulating film 183 onthe sidewalls of the gate electrodes 181 and 182. The material of thefirst interlayer insulating film to be the sidewall is preferably asilicon oxide film. The thickness may be 30 nm.

[0069] Then, using a resist mask, the element region for n channeltransistors in the memory cell portion 180 and the peripheral circuitportion 190 is selectively implanted with n type impurity ions. In thememory cell portion 180, phosphorus ions are implanted with an energy of7 keV, with a dose of 1×10¹³/cm² to form the n type diffusion layer 164to be a source/drain region of a MOSFET. Similarly, in the peripheralcircuit portion 190, using a resist mask, arsenic ions is for exampleimplanted with an energy of 10 keV, with a does of 1×10¹⁴/cm² to formthe n type diffusion layer 165 to be a source/drain region of a MOSFET.Note that a p channel transistor in each region may be similarly formedby implanting p type impurity ions such as B⁻ or BF²⁺ (not shown).

[0070] As shown in FIG. 6B, in order to form a second gate sidewallinsulating film, a silicon oxide film is formed to have a thickness inthe range from 20 to 100 nm. Here, the thickness is 70 nm. Subsequently,similarly to the case of forming the first sidewall insulating film 183,the silicon oxide film is etched back to form a second sidewallinsulating film 184 on the outer side of the first sidewall insulatingfilm 183. Here, in the memory cell portion 180, the second sidewallinsulating film 184 still fills the region between adjacent gateelectrodes 181 after the etch back step because the interval between thegate electrodes 181 is small and a sidewall will not form. Then, using aresist mask, n type impurity ions are implanted to the element regionfor n channel transistors in the peripheral circuit portion 190,followed by thermal treatment. Thus, an n type diffusion layer(source/drain) 188 of a high concentration is formed. The n typediffusion layer 188 may be formed for example by implanting As+ions withan implantation energy of 30 keV, with an implantation dose of3×10¹⁵/cm², followed by thermal treatment at a temperature of 750° C. ina nitrogen atmosphere.

[0071] As shown in FIG. 6C, a silicon nitride film is formed as anetching stopper film 185 to have a thickness of 20 nm on the entiresurface of the semiconductor substrate 161 having these elements formedthereon by low pressure CVD (Chemical Vapor Deposition). The stopperfilm 185 is in contact only with the upper surface of the first andsecond sidewall insulating films in the memory cell portion 180, whilein the peripheral circuit portion 190, the film is also in contact withthe semiconductor substrate 161.

[0072] As shown in FIG. 7A, a TEOS (tetraethylorthosilicate ortetraethoxysilane (Si(OC₂H₅)₄)) film is formed on the stopper film 185by CVD as an interlayer insulating film 166. Then, the surface of theinterlayer insulating film 166 is planarized as required. A CMP methodis preferably employed therefor.

[0073] Then, as shown in FIG. 7B, a photolithography technique and a dryetching technique are combined to form a contact hole. First, by thephotolithography technique, a resist mask (not shown) is formed on theinterlayer insulating film 166. The contact hole size in the memory cellportion 180 is smaller than that in the peripheral circuit portion 190.The contact hole in the memory cell contact 167 may have a size of 0.1μm for example, and the contact hole size in the peripheral circuitportion 168 may be 0.15 μm. Then, by dry etching, a contact hole isformed. The dry etching preferably includes two or more steps effectivefor etching. In the first step, the etching rate difference is smallbetween the interlayer insulating film 166 and the stopper film 185until the etching stopper film 185 in the memory cell portion 180 ispenetrated through. Thus, when the stopper film 185 in the memory cellportion 180 is removed in the contact hole, the stopper film 185 and theinterlayer insulating film 166 still remain in the peripheral circuitportion 190. In the second step, the interlayer insulating film 166 isetched by dry etching so that the contact hole in the memory cellportion 180 is completely open. Here, regarding the etching condition, ahigh selectivity ratio with the stopper film 185 is employed. When thecontact hole is completely open in the memory cell portion 180, at leastthe stopper film 185 of the nitride film remains in the peripheralcircuit portion 190.

[0074] Also as shown in FIG. 7B, the peripheral circuit portion contact168 is formed between the gate electrodes 182 and a contact having thesame shape as the peripheral circuit portion contact 168 is also formednext to gate electrodes 182 with no adjacent gate electrode 182. Thus,the peripheral circuit portion contacts 168 according to this embodimentare not necessarily limited to those formed between the gate electrodes182.

[0075] As shown in FIG. 7C, a silicon film 170 is selectively formed inthe hole for the memory cell contact 167. A selective epitaxy method maybe employed therefor. A fracture layer at the bottom surface of thecontact formed when the memory cell portion contact 167 is formed andresidue generated by the dry etching process or the like are removedaway by a wet cleaning process. Immediately before a growth process, anative oxide film on the bottom surface of the contact is removed awayby hydrofluoric acid. In these steps, the stopper film 185 in theperipheral circuit portion contact 168 is not removed, and therefore thesemiconductor substrate 161 is not exposed at the bottom of theperipheral circuit portion contact 168. Then, a selective epitaxialgrowth process is performed to form a silicon film 170 having athickness about in the range from 50 to 100 nm only in the hole for thememory cell portion contact 167.

[0076] The silicon film 170 may be compound crystal of silicon andgermanium. This can reduce the contact resistance.

[0077] The silicon film 170 is implanted with an impurity as follows. Inthe present embodiment, an n type transistor is provided in the memorycell portion 180. Therefore, phosphorus or arsenic may be introducedduring the growth of the silicon film or ions implantation may beperformed after the film is formed. In the former case, compound crystalof silicon and germanium may be used to improve the activationefficiency of the impurity, which effectively reduces the plugresistance. If both p and n type devices are provided in the memory cellportion 180 and n type doping is performed during forming the siliconfilm, a PN junction forms between the source/drain diffusion layer of ap type transistor and the silicon film. Therefore, a silicon film notdoped with an impurity is formed and then using a resist mask, thesilicon film in an n type transistor is implanted with phosphorus orarsenic ions.

[0078] Then, as shown in FIG. 8A, the stopper film 185 remaining at thebottom of the peripheral circuit portion contact 168 is selectivelyremoved away by dry etching. Thus, the n type diffusion layer 188 isexposed at the bottom of the peripheral circuit portion contact 168.

[0079] As shown in FIG. 8B, a metal plug is filled within the contactholes in the memory cell portion 180 and the peripheral circuit portion190. A titanium film is formed in contact with the silicon, and atitanium nitride film is formed on the titanium film. This film isthermally treated at an appropriate temperature, so that the titaniumreacts with the underlying silicon to form titanium silicide (TiSi₂).Thus, in the electrical contact characteristic, an ohmic contact resultsin the interface between the titanium silicide and the silicon film 170or the n type diffusion layer 188. After the thermal treatment forsilicidation reaction, a tungsten film is formed by CVD. The thicknessis preferably about in the range from 400 to 500 nm. When the part ofthese metal films above the upper surface of the contact opening isremoved by dry etching or CMP to provide the filled contact holes, anupper metal plug 173 is filled in the memory cell contact 167 on thesilicon film 170. Meanwhile, a metal plug 174 is filled in theperipheral circuit portion contact 168.

[0080] Then, as shown in FIG. 8C, a titanium or titanium nitride film isformed by sputtering or CVD. Furthermore, after an aluminum film isformed, using a resist mask, the aluminum film, the titanium nitridefilm and the titanium film are sequentially etched to form a desiredinterconnection structure.

[0081] The method of manufacturing the fifth embodiment has thefollowing effects.

[0082] 1. The contact resistance can be reduced without increasing thenumber of exposure steps.

[0083] 2. The contact resistance of a capacitance element to thesubstrate can be reduced.

[0084] 3. When the impurity concentration of the source/drain diffusionlayer in the memory cell portion is low (n⁻ or p⁻), the contactresistance to the diffusion layers can be reduced, while preventingcurrent leakage from increasing.

[0085] The effects are considered to result for the following reason.

[0086] In the region such as the memory cell portion 180 with a smallgate electrode interval, the space between the gate electrodes 181 isfilled with the second sidewall insulating film 184. Using thischaracteristic, etch back is performed at an appropriately controlledselectivity ratio, and the stopper film 185 is allowed to remain so asnot to expose the semiconductor substrate 161 in the peripheral circuitportion 190. As a result, the silicon film 170 can be selectively formedonly in the memory cell portion 180. The selectively formed silicon film170 allows the diffusion layer in the memory cell portion 180 to have alow concentration. The low concentration diffusion layer is necessaryfor a DRAM memory cell transistor or the like. If a metal plug contactthrough metal silicide is formed there, current leakage increases, whichincreases the contact resistance. If such a selectively formed siliconfilm is doped in a high concentration, the characteristic of the memorycell transistor will not be damaged, and yet a metal plug contact can beformed through silicide while preventing the current leakage fromincreasing.

[0087] Now, a sixth embodiment of the present invention will bedescribed. FIG. 9 is a cross sectional view of a semiconductor deviceaccording to the embodiment. Formed on a semiconductor substrate 201 area p well 202, an element isolation insulating film 203, and n typediffusion layers 204, 228 for a MOSFET in a memory cell 220 and aperipheral circuit portion 230. Also formed on the semiconductorsubstrate 201 are a gate insulating film 222, gate electrodes 221 and222 in the memory cell portion 220 and the peripheral circuit portion230, respectively and first and second sidewall insulating films 223 and224 on the sidewalls of the gate electrodes 221 and 222, similarly tothe fifth embodiment. Further, an etching stopper film 225 and aninterlayer insulating film 200 are sequentially formed thereon. Alsoaccording to the present embodiment, gate electrodes for MOSFETs areformed in a high density similarly to the memory cell portion 180according to the fifth embodiment. The impurity concentration of the ntype diffusion layer 204 to be a source/drain for a MOSFET in the memorycell portion 220 is preferably about in the range from 1 to 9×10⁸/cm³.

[0088] A memory cell portion contact 207 connected to the n typediffusion layer 204 is formed in the interlayer insulating film 200 onthe n type diffusion layer 204, the lower portion of which is filledwith a silicon film 210, and the upper portion is filled with an uppermetal plug 213. Among the two n type diffusion layers 204 for the MOSFETin the memory cell portion 220, one is connected to a lower electrode232 of a capacitive element through a capacitive plug 229. The other isconnected to a metal interconnection 195. In this case, the silicon film210 provided at the bottom of the contact is preferably doped in a highconcentration. An interlayer insulating film 236 is formed on a metalinterconnection 215, and the capacitive element connected to thecapacitive plug 229 is formed as described above. The capacitive elementincludes the lower electrode 232, a capacitive insulating film 233thereon and an upper electrode 234 thereon. The lower electrode 232 ofthe capacitive element may be for example of tungsten, while tantalumoxide for example may be used for the capacitive insulating film 233.Titanium nitride for example may be used for the upper electrode (plateelectrode) 234.

[0089] In the interlayer insulating film 200 on the n type diffusionlayer 228 in the peripheral circuit portion 230, a peripheral circuitportion contact 208 connected to the n type diffusion layer 228 isformed, into which a metal plug 214 is filled. The metal film to formthe upper metal plug 213 and the metal plug 214 to fill the contacts maybe tungsten similarly to the fifth embodiment. Note that the peripheralcircuit portion 230 and the n type diffusion layer 228 formed thereinare the same as those in the fifth embodiment.

[0090] Also in this embodiment, using the difference in the insulatingfilm structures of the contact openings similarly to the fifthembodiment, a polysilicon film plug is formed only at the bottom of thememory cell portion contact 207, while the peripheral circuit portioncontact 208 is directly connected with the diffusion layer 228 by themetal plug 214. As a result, without additional lithography process,contact openings on the n type diffusion layer in the memory cellportion 220 and the n type and p type diffusion layers in the peripheralcircuit portion 230 can be formed and a conductive material can befilled into the contacts at the same time in a series of process steps.The manufacturing steps can be simplified while the resistance of thememory cell portion contact 207 is reduced. The interconnectionarrangement in the peripheral circuit portion 230 can be simplified aswell, so that restriction upon size reduction in the peripheral circuitportion 230 can be removed. Furthermore, the series of process steps canbe executed without degrading the leakage characteristic of the contactportion in the memory cells. In addition, in this structure, a barrierfilm may be placed under the metal film plug in order to further reducethe contact resistance.

[0091] While there has been described what are at present considered tobe preferred embodiments of the invention, it will be understood thatvarious modifications may be made thereto, and it is intended that theappended claims cover all such modifications as fall within the truespirit and scope of the invention.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising the steps of: forming first and second diffusion layers on asurface of a semiconductor substrate; forming an interlayer insulatingfilm on said semiconductor substrate including said first and seconddiffusion layers; forming first and second openings in a region of theinterlayer insulating film on said first diffusion layer and a region ofthe interlayer insulating film on said second diffusion layer,respectively to expose surfaces of said first and second diffusionlayers; depositing a conductive silicon film on said semiconductorsubstrate; etching back said conductive silicon film to form a lowerportion of a first plug in a lower portion of said first opening whileat the same time removing the conductive silicon film at the bottom ofsaid second opening to expose a surface of said second diffusion layer;and depositing a metal film on said semiconductor substrate includingsaid first and second openings, filling said first and second openingswith said metal film to form an upper portion of said first plug on saidlower conductive silicon plug in said first opening while at the timefilling said metal film in said second opening to form a second plug. 2.The method of manufacturing a semiconductor device according to claim 1,wherein said depositing said metal film comprises the steps of:depositing a barrier metal film on said semiconductor substrateincluding said first and second openings; and depositing a metal filmlapped on said barrier metal film.
 3. The method of manufacturing asemiconductor device according to claim 1, wherein the opening width ofsaid first opening is smaller than twice the thickness of saidconductive silicon film; and the opening width of said second opening islarger than twice the thickness of said conductive silicon film.
 4. Themethod of manufacturing a semiconductor device according to claim 1,wherein said conductive silicon film is of one kind selected from thegroup consisting of a polysilicon film, an amorphous silicon film, anepitaxially grown film, and a silicon-germanium compound crystal film.5. The method of manufacturing a semiconductor device according to claim1, wherein said conductive silicon film is an amorphous silicon film,and further comprising the step of reforming said amorphous silicon filminto a polysilicon film after filling said second opening with saidmetal film.
 6. A method of manufacturing a semiconductor device,comprising the steps of: forming first and second diffusion layers on asurface of a semiconductor substrate; forming an interlayer insulatingfilm on said semiconductor substrate including said first and seconddiffusion layers; forming a first opening in a region of the interlayerinsulating film on said first diffusion layer to expose a surface ofsaid first diffusion layer; depositing a conductive silicon film to filla lower portion of said first opening with said conductive silicon film,thereby forming a lower portion of a first plug; depositing an uppermetal film to fill an upper portion of said first opening with saidupper metal film, thereby forming an upper portion of said first plug;forming a second opening in a region of the interlayer insulating filmon said second diffusion layer to expose a surface of said seconddiffusion layer; and depositing a metal film on said semiconductorsubstrate including said second opening to fill said second opening withsaid metal film, thereby forming a second plug.
 7. The method ofmanufacturing a semiconductor device according to claim 6, wherein saidfilling said first opening with the conductive silicon film comprisesthe steps of: depositing the conductive silicon film on saidsemiconductor substrate including said first opening; and etching backsaid conductive silicon film.
 8. The method of manufacturing asemiconductor device according to claim 6, wherein said depositing saidupper metal film filled within said first opening and said metal filmfilled within said second opening comprise the steps of: depositing abarrier metal film on said semiconductor substrate including said firstand second openings; and depositing a metal film lapped on saidsemiconductor including said first and second openings.
 9. The method ofmanufacturing a semiconductor device according to claim 6, wherein saidconductive silicon film is of one kind selected from the groupconsisting of a polysilicon film, an amorphous silicon film, anepitaxially grown film and a silicon-germanium compound crystal film.10. The method of manufacturing a semiconductor device according toclaim 6, wherein said conductive silicon film is an amorphous siliconfilm, and further comprising the step of reforming said amorphoussilicon film into a polysilicon film after filling said second openingwith said metal film.
 11. A method of manufacturing a semiconductordevice, comprising the steps of: forming first and second diffusionlayers on a surface of a semiconductor substrate; forming an interlayerinsulating film on said semiconductor substrate including said first andsecond diffusion layers; forming first and second openings in a regionsin the interlayer insulating film on said first and second diffusionlayers, respectively and exposing only a surface of said first diffusionlayer; depositing a conductive silicon film to fill a lower portion ofsaid first opening with the conductive silicon film, thereby forming alower portion of a first plug; exposing a surface of said seconddiffusion layer at the bottom of said second opening; and depositing ametal film on said semiconductor substrate including said first andsecond openings, filling an upper portion of said first opening withsaid metal film to form an upper portion of said first plug, while atthe same time filling said second opening with said metal film to form asecond plug.
 12. The method of manufacturing a semiconductor deviceaccording to claim 11, wherein said depositing said metal film on saidsemiconductor substrate including said first and second openingscomprises the steps of: depositing a barrier metal film on saidsemiconductor substrate including said first and second openings; anddepositing a metal film lapped on said semiconductor including saidfirst and second openings.
 13. The method of manufacturing asemiconductor device according to claim 11, wherein said conductivesilicon film is of one kind selected from the group consisting of apolysilicon film, an amorphous silicon film, an epitaxially grown filmand a silicon-germanium compound crystal film.
 14. The method ofmanufacturing a semiconductor device according to claim 11, wherein saidconductive silicon film is an amorphous silicon film, and furthercomprising the step of reforming said amorphous silicon film into apolysilicon film after filling said second opening with said metal film.15. The method of manufacturing a semiconductor device according toclaim 11, further comprising the steps of: forming a sidewall insulatingfilm at a sidewall of a gate electrode before forming said interlayerinsulating film; and forming an etching stopper film on said sidewallinsulating film.
 16. The method of manufacturing a semiconductor deviceaccording to claim 15, wherein said forming said first and secondopenings and exposing only a surface of said first diffusion layercomprises the step of allowing said etching stopper film positioned atsaid second opening to remain.
 17. The method of manufacturing asemiconductor device according to claim 15, wherein said sidewallinsulating film is a film to protect a side surface of said gateelectrode, the opening width of said first opening is smaller than twicethe thickness of said sidewall insulating film and the opening width ofsaid second opening is larger than twice the thickness of said sidewallinsulating film.
 18. The method of manufacturing a semiconductor deviceaccording to claim 16, wherein said exposing a surface of the seconddiffusion layer at said second opening is executed by removing saidetching stopper film positioned at said second opening.
 19. A method ofmanufacturing a semiconductor device, comprising the steps of: formingfirst and second gate electrodes on a semiconductor substrate, thedistance between said first gate electrodes being narrow than thedistance between said second gate electrodes; forming a first sidewallinsulating film at sidewalls of said first and second gate electrodes;forming a first diffusion layer on said semiconductor substrate usingsaid first gate electrode and said first sidewall insulating film as amask and forming a second diffusion layer on said semiconductorsubstrate using said second gate electrode and said first sidewallinsulating film as a mask; forming a second sidewall insulating film onsaid first sidewall insulating film; depositing an etching stopper film;forming an interlayer insulating film on said etching stopper film;etching said interlayer insulating film, said etching stopper film andsaid first and second sidewall insulating film so as to form a firstopening in a region on said first diffusion layer exposing a surface ofsaid first diffusion layer and a second opening in a region on saidsecond diffusion layer exposing said etching stopper film; depositing aconductive silicon film to fill a lower portion of said first openingwith the conductive silicon film, thereby forming a lower portion of afirst plug; removing said etching stopper film at the bottom of saidsecond opening to expose a surface of said second diffusion layer; anddepositing a metal film on said semiconductor substrate including saidfirst and second openings, filling an upper portion of said firstopening with said metal film to form an upper portion of said first plugin said first opening while at the same time filling said second openingwith said metal film to form a second plug in said second opening. 20.The method of manufacturing a semiconductor device according to claim19, wherein said conductive silicon film is of one kind selected fromthe group consisting of a polysilicon film, an amorphous silicon film,an epitaxially grown film, and a silicon-germanium compound crystalfilm.
 21. The method of manufacturing a semiconductor device accordingto claim 19, wherein said conductive silicon film is an amorphoussilicon film, and further comprising the step of reforming saidamorphous silicon film into a polysilicon film after filling said secondopening with said metal film.